A sequential conversion type analog to digital (AD) converter holds an input analog signal, and performs comparison processing to compare the held analog signal with a comparative voltage repetitively for every bit to thereby obtain a digital signal as a conversion result (see, for example, Japanese Patent Application Publication No. 2013-191976 (Patent Literature 1)). In the comparison processing, a comparative voltage for the next bit comparison needs to be generated using a digital to analog (DA) converter, and noise may be produced in the generation of the comparative voltage. In an approach proposing improvement in conversion accuracy, the comparison processing for the next bit is performed not immediately after the comparison processing for the previous bit, but after noise produced during the generation of the comparative voltage settles down (e.g., after waiting one clock).
However, when an AD conversion device includes a plurality of sequential conversion type AD converters that operate independently of one another, noise produced in a certain sequential conversion type AD converter affects the comparison processing performed by another AD converter. This poses a problem of degradation in the conversion accuracy. If the sequential conversion type AD converters are synchronized, noise can be controlled not to be produced in the comparison processing. This, however, puts load on a higher-level device which needs to control the synchronization of the AD converters.